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19-5502; Rev 9/10
DS1744/DS1744P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations. Century Byte Register (i.e., Y2K Compliant) Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap-Year Compensation Valid Up to the Year 2100 Battery Voltage-Level Indicator Flag Power-Fail Write Protection Allows for 10% VCC Power-Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time DIP Module Only Standard JEDEC Byte-Wide 32k x 8 Static RAM Pinout PowerCap Module Board Only Surface-Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-On Reset Output Pin-for-Pin Compatible with Other Densities of DS174xP Timekeeping RAM Also Available in Industrial Temperature Range: -40C to +85C UL Recognized
PIN CONFIGURATIONS
TOP VIEW

A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
1 28 2 DS1744 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15
VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
EDIP
N.C. N.C. N.C. RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
DS1744P
X1
GND
VBAT
X2
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18
N.C. N.C. A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
PowerCap MODULE BOARD (Uses DS9034PCX PowerCap)

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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
EDIP 1 2 3 4 5 6 7 8 9 10 21 23 24 25 26 11 12 13 15 16 17 18 19 14 20 22 27 28 -- -- -- PIN PowerCap 32 30 25 24 23 22 21 20 19 18 28 29 27 26 31 16 15 14 13 12 11 10 9 17 8 7 6 5 4 1, 2, 3, 33, 34 NAME A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 A10 A11 A9 A8 A13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND CE OE WE VCC RST N.C. X1, X2, VBAT FUNCTION
Address Input
Data Input/Output
Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input Active-Low Reset Output, Open Drain. Requires a pullup resistor for proper operation. No Connection Crystal Connections, VBAT Battery Connection
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
VOLTAGE (V) DS1744-70+ 5.0 DS1744-70IND+ 5.0 DS1744W-120+ 3.3 DS1744W-120IND+ 3.3 DS1744P-70+ 5.0 DS1744P-70IND+ 5.0 DS1744WP-120+ 3.3 DS1744WP-120IND+ 3.3 PART
+Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately). **A "+" anywhere in the top mark denotes a lead-free device. An "IND" denotes an industrial temperature grade device.
TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C
PIN-PACKAGE 28 EDIP 28 EDIP 28 EDIP 28 EDIP 34 PowerCap* 34 PowerCap* 34 PowerCap* 34 PowerCap*
TOP MARK** DS1744+70 DS1744+70 IND DS1744W+120 DS1744W+120 IND DS1744P+70 DS1744P+70 IND DS1744WP+120 DS1744WP+120 IND
DESCRIPTION
The DS1744 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 32k x 8 NV SRAM. User access to all registers within the DS1744 is accomplished with a byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1744 also contains its own power-fail circuitry that deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. DS1744/DS1744P Block Diagram
DS1744/DS1744P
PACKAGES
The DS1744 is available in two packages (28-pin encapsulated DIP and 34-pin PowerCap module). The 28-pin EDIP module integrates the crystal, lithium energy source, and silicon all in one package. The 34pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1744P after the completion of the surface-mount process. Mounting the PowerCap after the surface-mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
CLOCK OPERATIONS--READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register (Table 2). As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is, day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All the DS1744 registers are updated simultaneously after the internal clock-register updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The READ bit must be a 0 for a minimal of 500s to ensure the external registers are updated.
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table CE VCC VIH VIL VCC > VPF VIL VIL VSO < VCC < VPF X VCC < VSO < VPF X
OE X X VIL VIH X X
WE X VIL VIH VIH X X
MODE Deselect Write Read Read Deselect Deselect
DQ High-Z Data In Data Out High-Z High-Z High-Z
POWER Standby Active Active Active CMOS Standby Data-Retention Mode
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the DS1744 registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator can be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers (Table 2). Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register toggles at 512Hz. When the seconds register is being read, the DQ0 line toggles at the 512Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable).
CLOCK ACCURACY (DIP MODULE)
The DS1744 is guaranteed to keep time accuracy to within 1 minute per month at +25C. The RTC is calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also affected by the electrical environment; caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
CLOCK ACCURACY (PowerCap MODULE)
The DS1744 and DS9034PCX are individually tested for accuracy. Once mounted together, the module typically keeps time accuracy to within 1.53 minutes per month (35ppm) at +25C. Clock accuracy is also affected by the electrical environment and caution should be taken to place the RTC in the lowestlevel EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS 7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8
OSC = Stop Bit W = Write Bit
B7 X X BF X X OSC W
B6 10 Year X X FT X
B5
DATA B4
B3
B2 Year Month Date
B1
B0
FUNCTION Year Month
RANGE 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-39
R
10 X Month 10 Date X X 10 Hour 10 Minutes 10 Seconds 10 Century
R = Read Bit X = See Note
X
Day Hour Minutes Seconds Century
FT = Frequency Test BF = Battery Flag
Date Day Hour Minutes Seconds Century
Note: All indicated "X" bits are not used but must be set to a "0" during write cycle to ensure proper clock operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data is available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and states are not met, valid data is available at the latter of chip-enable access (tCEA) or at output-enable access time (tOEA). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time (tOH) but then goes indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE then disables the output tWEZ after WE goes active.
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the internal clock registers and SRAM are blocked from any access. At this time the power-fail reset-output signal ( RST ) is driven active and remains active until VCC returns to nominal levels. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible, and data can be written or read only when VCC is greater than VPF. When VCC falls below VPF access to the device is inhibited. At this time the power-fail reset-output signal ( RST ) is driven active and remains active until VCC returns to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The RST signal is an open-drain output and requires a pullup. Except for the RST , all control, data, and address signals must be powered down when VCC is powered down.
BATTERY LONGEVITY
The DS1744 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1744 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running in the absence of VCC power. Each DS1744 is shipped from Maxim with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1744 is much longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1744 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of the day register is used to indicate the voltage-level range of the battery. This bit is not writable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are questionable.
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground...........................................................................-0.3V to +6.0V Storage Temperature Range EDIP......................................................................................................................-40C to +85C PowerCap............................................................................................................-55C to +125C Lead Temperature (soldering, 10s)................................................................................................................+260C Note: EDIP is hand or wave-soldered only. Soldering Temperature (reflow, PowerCap).................................................................................................................+260C
This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
OPERATING RANGE
RANGE Commercial Industrial
(TA = Over the operating range)
TEMP RANGE 0C to +70C, Noncondensing -40C to +85C, Noncondesnsing
VCC 3.3V 10% or 5V10% 3.3V 10% or 5V10%
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Logic 1 Voltage (All Inputs) VCC = 5V 10% VCC = 3.3V 10% Logic 0 Voltage (All Inputs) VCC = 5V 10% VCC = 3.3V 10% SYMBOL VIH VIH VIL VIL MIN 2.2 2.0 -0.3 0.3 TYP MAX VCC + 0.3V VCC + 0.3V 0.8 0.6 UNITS V V V V 1 NOTES 1
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER Active Supply Current TTL Standby Current ( CE = VIH) CMOS Standby Current ( CE VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT = +2.1mA) Write Protection Voltage Battery Switchover Voltage
SYMBOL ICC ICC1 Icc2 IIL IOL VOH VOL VPF VSO
MIN
TYP
MAX 75 6 4
UNITS mA mA mA A A
NOTES 2, 3, 10 2, 3 2, 3
-1 -1 2.4
+1 +1
1 0.4 1 V 1 1, 4
4.25 VBAT
4.50
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER Active Supply Current TTL Standby Current ( CE = VIH) CMOS Standby Current ( CE VCC - 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT = +2.1mA) Write Protection Voltage Battery Switchover Voltage
SYMBOL ICC ICC1 ICC2 IIL IOL VOH VOL VPF VSO
MIN
TYP
MAX 30 2 2
UNITS mA mA mA A A
NOTES 2, 3, 10 2, 3 2, 3
-1 -1 2.4
+1 +1
1 0.4 1 V V 1 1, 4
2.80 VBAT or VPF
2.97
AC CHARACTERISTICS--READ CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the operating range.) PARAMETER Read Cycle Time Address Access Time
CE to DQ Low-Z CE Access Time CE Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time
SYMBOL tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH
MIN 70
TYP
MAX
UNITS ns
NOTES
70 5 70 25 5 35 25 5
ns ns ns ns ns ns ns ns
Output Hold from Address
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS--READ CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER Read Cycle Time Address Access Time
CE to DQ Low-Z CE Access Time CE Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time
SYMBOL tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH
MIN 120
TYP
MAX
UNITS ns
NOTES
120 5 120 40 5 100 35 5
ns ns ns ns ns ns ns ns
Output Hold from Address
READ CYCLE TIMING DIAGRAM
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS--WRITE CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER Write Cycle Time Address Setup Time
WE Pulse Width CE Pulse Width
SYMBOL tWC tAS tWEW tCEW tDS tDH1 tDH2 tAH1 tAH2 tWEZ tWR
MIN 70 0 50 60 30 0 0 5 5
TYP
MAX
UNITS ns ns ns ns ns ns ns ns ns
NOTES
Data Setup Time Data Hold Time Data Hold Time Address Hold Time Address Hold Time
WE Data Off Time
8 9 8 9
25 5
ns ns
Write Recovery Time
AC CHARACTERISTICS--WRITE CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER Write Cycle Time Address Setup Time
WE Pulse Width CE Pulse Width CE and CE2 Pulse Width
SYMBOL tWC tAS tWEW tCEW tCEW tDS tDH1 tDH2 tAH1 tAH2 tWEZ tWR
MIN 120 0 100 110 110 80 0 0 0 10
TYP
MAX
UNITS ns
NOTES
120
ns ns ns ns ns ns ns ns ns 8 9 8 9
Data Setup Time Data Hold Time Data Hold Time Address Hold Time Address Hold Time
WE Data Off Time
40 10
ns ns
Write Recovery Time
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN AC CHARACTERISTICS (5V)
(VCC = 5.0V 10%, TA = Over the operating range.)
PARAMETER
CE or WE at VIH Before Power-Down
SYMBOL tPD tF tFB tR tREC tDR
MIN 0 300 10 0
TYP
MAX
UNITS s s s s
NOTES
VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Fall Time: VPF(MIN) to VSO VCC Rise Time: VPF(MIN) to VPF(MAX) Power-Up Recover Time Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN TIMING (5V DEVICE)
35 10
ms years 5, 6
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS (3.3V)
(VCC = 3.3V 10%, TA = Over the operating range.)
PARAMETER
CE or WE at VIH, Before PowerDown
SYMBOL tPD tF tR tREC tDR
MIN 0 300 0
TYP
MAX
UNITS s s s
NOTES
VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data-Retention Time (Oscillator ON)
35 10
ms years 5, 6
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25C) PARAMETER Capacitance On All Input Pins Capacitance On All Output Pins SYMBOL CIN CO MIN TYP MAX 14 10 UNITS pF pF NOTES
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate Input Pulse Levels: 0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground. 2) Typical values are at +25C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF. 5) Data-retention time is at +25C. 6) Each DS1744 has a built-in switch that disconnects the lithium source until the user first applies VCC. The expected tDR is defined for DIP modules and assembled PowerCap modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 7) RTC modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap: a. ) Maxim recommends that PowerCap module bases experience one pass through solder reflow oriented with the label side up ("live-bug"). b.) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove solder. 8) tAH1, tDH1 are measured from WE going high. 9) tAH2, tDH2 are measured from CE going high. 10) tWC = 200ns.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 28 EDIP 34 PWRCP
PACKAGE CODE MDF28+3 PC2+2
DOCUMENT NO. 21-0245 21-0246
LAND PATTERN NO. -- --
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DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
REVISION HISTORY
REVISION DATE DESCRIPTION Updated the Ordering Information table to include only lead-free parts; updated the Absolute Maximum Ratings section to include the storage temperature range and lead and soldering temperatures for EDIP and PowerCap packages; added Note 10 to the ICC parameter in the DC Electrical Characteristics tables (for 5.0V and 3.3V) and the Notes section; updated the Package Information table PAGES CHANGED
9/10
3, 8, 9, 15
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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2010 Maxim Integrated Products Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products.

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